Reducing Clearing Time
The TCC bridge — faster trip = less energy. ARMS/RELT, ZSI, NEC 240.87.
Arc-flash incident energy is roughly linear in clearing time. If you can cut the upstream device’s clearing time in half, you cut the energy at the worker in half. That’s the most powerful lever an engineer has — and it’s exactly the curve you’ve been adjusting on every TCC plot in the coordination tutorial.
The catch: the reason coordination engineers set long-time and short-time delays in the first place is to let downstream devices clear before the upstream picks up. Killing the delay to reduce arc-flash energy can wreck selective coordination. The good news is that several techniques resolve that tension. ARMS / RELT, ZSI, and NEC 240.87 are the standard answers.
Watch the energy track the curve
The widget below has a 2000 A LVPCB main with its instantaneous OFF and its short-time delay set to 300 ms. That’s a typical “coordinated service main” configuration — slow enough that any downstream feeder breaker can clear first.
The downside is visible immediately. At a 25 kA bus fault, the main’s clearing time is 300 ms, and the arc-flash label below the plot reads somewhere in Category 3 (around 8.7 cal/cm²).
The vertical line on the plot marks the fault current. The upstream device's curve at that current sets the clearing time below.
The cyan vertical line on the plot marks the bus Isc — drag the slider to move it. The clearing time the arc-flash calculator uses is the upstream LVPCB’s curve at that current.
Try this — turn instantaneous on
Drag the I pickup slider up from 0 (OFF) to 8× (16 000 A). At 25 kA, the fault is now above I pickup, so the LVPCB trips in its instantaneous region — about 20 ms of trip-unit reaction time on the simplified curve.
Watch the arc-flash label below the plot. Incident energy drops from ~8.7 cal/cm² to under 1 cal/cm² — you just moved from Cat 3 down to below the arc-rated-PPE threshold (under 1.2 cal/cm² — no arc rating required for the task) without changing a thing about the system impedance.
In real installations, the breaker’s mechanical opening time adds 3 – 5 cycles (~50 – 80 ms) on top of the trip unit’s reaction. Total clearing in the 70 – 100 ms range is typical, which puts actual incident energy in the ~2 – 3 cal/cm² range — Cat 1 in practice. The widget shows the trip-unit-only case; the direction of the improvement is what matters.
The catch shows up immediately on the TCC plot: the LVPCB’s instantaneous region now overlaps anything downstream that was being coordinated by the 300 ms S delay. A 800 A feeder LVPCB below this main, with its own S pickup at 4× (3200 A), would lose coordination on any fault between ~3.2 kA and 25 kA — both devices would trip together.
That’s the tension between coordination and arc-flash energy in one plot. The next three techniques resolve it.
Technique 1 — ARMS / RELT / maintenance switches
ARMS = “Arc-flash Reduction Maintenance System” (Eaton’s trademark). RELT = “Reduce Energy Let-Through” (GE / ABB / Square D variants). All the brands describe the same idea: a maintenance-mode switch on the upstream breaker that temporarily makes its instantaneous much faster (or activates instantaneous at a lower pickup), only while a worker is in front of the equipment.
Operating principle:
- Worker arrives at downstream equipment.
- Before opening the energized cabinet, worker reaches up to the upstream main / feeder breaker and flips the ARMS switch ON.
- The upstream breaker’s instantaneous pickup drops (e.g. from “OFF / 10×” to “2.5×”) OR a special “no-intentional-delay” mode is enabled.
- Worker performs the energized task. Any fault during the work clears in 1–2 cycles instead of S-delay seconds.
- Worker leaves, flips ARMS off, normal coordination is restored.
Practical consequence: the arc-flash label on the equipment can show two energies — normal operation (high) and ARMS-mode (low). Workers wear PPE rated for the normal energy on first approach, flip the switch to ARMS, and the operational mode then matches their PPE.
ARMS is the cheapest fix when retrofitting an over-energy bus. It costs a few hundred to a few thousand dollars per breaker.
Technique 2 — Zone-selective interlocking (ZSI)
ZSI is the elegant fix. Each breaker has a signal output it asserts when its short-time element picks up, and a signal input from the breakers below it. The upstream breaker watches its downstream signals:
- If a downstream breaker is picked up, the upstream waits its full S delay — letting the downstream clear first. Coordination is preserved.
- If no downstream breaker is picked up, the upstream can’t be feeding into a downstream-cleared fault — the fault is on its zone — so it trips with no intentional delay.
Result: the upstream device gets near-instantaneous clearing on zone faults and full coordination delay on through-faults to downstream devices. Best of both worlds.
ZSI requires signal wiring between the breakers (typically a few twisted pairs of low-voltage cable per pair of breakers) and ZSI- compatible trip units. New construction with electronic trip units gets ZSI nearly for free. Retrofits are more expensive — sometimes prohibitive on older switchgear.
Technique 3 — Current-limiting fuses upstream
If the upstream protective device is a current-limiting fuse (J or L class), it goes into its current-limiting region within half a cycle at high faults. Clearing time is effectively sub-8 ms, regardless of the downstream coordination story.
This is how some legacy industrial installations get away with high available Isc and still pass arc-flash analysis: a properly-sized class-L fuse upstream of the work point caps the let-through and truncates the arc-flash duration. The selective coordination story is different (fuses don’t coordinate against breakers gracefully) — but the arc-flash story is solved.
NEC 240.87 — the code requirement
NEC 240.87, “Arc Energy Reduction,” applies wherever the highest continuous current trip setting the circuit breaker is rated for (or can be adjusted to) is 1200 A or higher — it’s triggered by the breaker’s trip rating, not by whether energized work is planned. Where it applies, the installation must document the breaker locations and demonstrate that the chosen method is set to operate below the available arcing current (240.87(A)), and provide one of the following means — each set to operate at less than the available arcing current — per 240.87(B):
- Zone-selective interlocking (ZSI)
- Differential relaying
- Energy-reducing maintenance switching with local status indicator (the ARMS / RELT family)
- Energy-reducing active arc-flash mitigation system (arc-flash relays with sensors)
- An instantaneous trip setting — the “turn INST on (low enough)” answer. The code does not allow merely temporarily nudging the instantaneous setting to claim the reduction; that’s what the maintenance switch (#3) or the override (#6) are for.
- An instantaneous override
- An approved equivalent means
Since the 2023 edition, 240.87(C) also requires the arc-energy-reduction system to be performance tested on site when first installed.
A 2000 A service main with none of these is not code-compliant under the current NEC. Many older installations grandfather under prior code editions, but new construction has to address 240.87 explicitly. NEC 240.67 is the fuse-side companion requirement.
A real coordination decision
A coordination engineer typically faces this question on every service main 1200 A and up:
| Approach | Coordination preserved? | Arc-flash energy reduction? | Cost | Code-compliant for 240.87? |
|---|---|---|---|---|
| Slow S delay, INST OFF | ✅ | ❌ | $0 | ❌ |
| INST ON at lowest pickup | ❌ (overlaps downstream) | ✅ | $0 | ✅ (method 5) |
| ARMS / RELT | ✅ (normal), ❌ (maintenance) | ✅ (maintenance) | $$ | ✅ (method 3) |
| ZSI | ✅ | ✅ | $$$ | ✅ (method 1) |
ZSI is the engineering ideal. ARMS/RELT is the budget answer. “INST ON, accept coordination loss” is the expedient answer when the arc-flash exposure is bad and the coordination loss is tolerable (and easier to argue with than a $30 000 retrofit).
What’s next
You’ve hit the end of the curriculum’s standard 7-lesson outline. The free-play sandbox lets you build any scenario — pick a bus, pick an upstream device, watch the arc-flash label respond to every slider.
This tutorial deliberately kept its worked examples at low voltage (≤ 600 V) — even though the IEEE 1584-2002 model itself spans 208 V – 15 kV — and left several adjacent areas (the MV / 15 kV end of that range in practice, NESC transmission work, DC arc flash, full multi-bus system analysis) for production tools — SKM, ETAP, EasyPower — and for the IEEE 1584-2018 standard itself.